Intel vs TSMC: the battle for chip supremacy

The semiconductor industry stands at a pivotal moment in its history, with Taiwan Semiconductor Manufacturing Company (TSMC) and Intel competing for dominance in advanced chip manufacturing. Both companies are racing to achieve breakthroughs in 1.6-nanometer (nm) technology, a development that promises to redefine computing, artificial intelligence (AI), and a host of other industries.
The competition between these two giants is not just about technological innovation but also about economic viability and strategic positioning. Understanding the dynamics of this rivalry is crucial for grasping the future of the semiconductor industry and its impact on various technological advancements. Let’s take a look at how these two companies are battling for the ultimate chip supremacy.
TSMC controls nearly 90% of the world’s chip production, cementing its place as the leading innovator in semiconductor technology. Since its inception in 1987, producing three-micron (3,000nm) chips, the company has continuously pushed technological boundaries. The introduction of 1.6 nm chips marks a monumental milestone, enabled by a novel transistor architecture and the integration of backside power delivery—two innovations poised to reshape the future of chip design.
To appreciate the significance of TSMC’s advancements, it’s crucial to understand the role of transistors. At the heart of semiconductor technology, transistors are tiny electrical switches that control current flow. Traditional FinFET transistors, which have been the industry standard, face physical limitations, particularly with leakage currents as they scale down in size. The FinFET structure, introduced commercially by Intel in 2011, provides better control over current flow. However, as these transistors approach the limits of their efficiency, a new architecture is necessary.
Following Intel’s initial success, Samsung and TSMC developed their own FinFET chips, advancing the technology to 16 nm and 14 nm nodes. Now, the industry is moving towards Gate-All-Around (GAA) transistors to further shrink transistors and improve efficiency. TSMC’s version, called ‘Nanosheet transistors’, improves upon the FinFET structure by wrapping the gate completely around the channel, providing superior control over the current flow. GAA transistors consume up to 35% less power compared to FinFET technology, enabling more compact and efficient chip layouts. TSMC’s upcoming A16 technology will leverage GAA transistors, along with a major enhancement—backside power delivery—that is set to revolutionise chip design.
Traditionally, both signal interconnects and power delivery are located on the front side of semiconductor wafers. TSMC’s introduction of backside power delivery moves the power mesh to the back of the wafer, freeing up space for signal routing on the front. This change allows for denser placement of transistors, reduces wiring complexity, and improves power efficiency. This separation of power and signal pathways is expected to improve not only chip density but also overall performance.
TSMC plans to begin mass-producing chips using its N2P and A16 technology, which includes backside power delivery, by 2026. But it is not alone in pursuing these innovations—Intel is also working on similar advancements and is aiming to bring the new transistor architecture and power delivery technology to market before TSMC.
Over the past five years, Intel has fallen behind both TSMC and Samsung in advanced chip manufacturing. Now, it sees an opportunity to reclaim leadership in the semiconductor industry. Intel is developing its own version of GAA transistors, known as RibbonFET, along with a backside power delivery technology dubbed PowerVia. These innovations will debut in Intel’s 20A process node.
However, Intel’s approach is risky. Introducing two revolutionary technologies—RibbonFET and PowerVia—simultaneously increases the likelihood of unforeseen challenges. Historically, new technologies are introduced incrementally to allow time for troubleshooting. Intel’s decision to combine both RibbonFET and PowerVia shows its willingness to take significant risks in its effort to leap ahead of TSMC.
Intel’s Arrow Lake CPUs will be the first to incorporate these technologies, but the real test will come with Intel’s 14A node, scheduled for 2027. This node will incorporate high numerical aperture (NA) EUV lithography machines from ASML, which will enable the printing of even finer transistor features. However, adopting these advanced machines presents high costs and risks to Intel’s economic strategy.
Extreme ultraviolet (EUV) lithography machines are essential for printing the tiny features needed in advanced process nodes. At advanced nodes beyond 3 nm, traditional EUV lithography machines face limitations, necessitating the use of complex and expensive multi-patterning techniques to achieve finer transistor features. To address this, Intel plans to adopt the new high NA EUV machines from ASML, which can achieve resolutions up to 8 nm, for its 14A node. TSMC, however, has decided to pass on the high NA machines for now, citing their high cost and limited fab throughput.
The semiconductor industry’s race toward smaller, more efficient chips isn’t just a technological competition—it’s also an economic one. While Moore’s Law is often viewed as a rule about shrinking transistors, its true purpose is improving cost-efficiency. The real challenge facing Intel and TSMC is not only in achieving technical breakthroughs but also in producing them at scale, with high yields, and at minimum cost.
TSMC has chosen a more cautious approach, focusing on cost-efficient manufacturing while keeping its innovations practical. In contrast, Intel is banking on cutting-edge technologies like direct self-assembly, which uses polymers to self-organise into nanoscale patterns on the wafer, to offset costs. However, this technology is still in its experimental phase, with high defect rates presenting a significant challenge.
Beyond the high NA EUV machines, the semiconductor industry is already looking towards hyper NA EUV machines and new transistor architectures. After GAA, fabs will transition to complementary FET (CFET) transistors. The idea of CFET is to fold two nanosheet transistors on top of each other vertically to build a CFET structure. Intel was the first company back in 2020 to make CFET work by stacking NMOS transistors on top of PMOS. In this way, they built the simplest logic circuit imaginable—a CFET inverter. When input is applied to such a circuit, its output is a logical inversion of the input. It’s clear that vertical transistors, together with backside power delivery, represent the future of transistors and silicon chips.
As we stand on the crossover of a new era in semiconductor technology, the competition between TSMC and Intel is about more than just innovation. It’s about navigating the delicate balance. Intel’s high-risk, high-reward approach with RibbonFET and PowerVia could potentially position it back at the forefront of the industry. However, TSMC’s steady, cost-conscious strategy may prove more sustainable in the long run.
The decisions made today by these semiconductor giants will shape the future of computing and technologies. Whether Intel’s bold bets or TSMC’s incremental innovations will win out remains to be seen, but one thing is clear: the next decade in semiconductor technology will be defined by who can achieve the next breakthrough—and at what cost.